As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One recent technique finding greater application in increasing packing density is to form field effect transistors in thin films which are vertically stacked on top of transistors in the bulk material, thus resulting in 3-D integration. This is commonly referred to as "thin film transistor" (TFT) technology.
With TFTs, a thin film of semiconductive material is first provided. A central channel region of the thin film is masked, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having active and channel regions formed entirely within a thin film, as opposed to utilizing bulk substrate material.
One common material utilized as the thin source, channel and drain film in a TFT is polycrystalline silicon. Such is composed of multiple orientations of individual single crystal silicon grains. The location where two individual crystalline grains abut one another is commonly referred to as a grain boundary. Grain boundaries are inherent in polycrystalline materials, such as polycrystalline silicon, as it is the boundaries which define the breaks between individual crystal grains. In a silicon lattice (or single crystal silicon), a silicon atom inherently tries to bond to four other silicon atoms. In polycrystalline silicon, the lattice structure breaks down at the grain boundaries giving rise to silicon atoms with dangling bonds. A collection of these dangling or "broken" bonds for a given crystal runs along a plane which defines the boundary for that crystal.
Conductivity in doped polycrystalline silicon, which is an overall function of carrier mobility, inherently depends upon the grain boundary trap density. The lower the grain boundary trap density, the greater the carrier mobility and accordingly the conductivity. Grain boundaries adversely affect inherent conductivity of the material due to the presence of a potential barrier at the grain boundaries which arises from carrier trapping. This barrier degrades conductivity by impeding the flow of carriers in an applied field. The greater the number of boundaries, the lower the conductance or the higher the resistance. Also, the larger the average crystalline grain size, the lower the total number of grain boundaries. Accordingly, the larger the crystal size, the greater the inherent conductivity of the polycrystalline material for a given doping concentration.
Unfortunately, it is typically easier to more uniformly control material properties the smaller the processor attempts to make the polycrystalline grains. Alternately considered, although lower resistance results from larger grain size, it is more difficult to uniformly and consistently control resistivity the larger one tries to make the crystals.
Grain boundaries also affect a property known as "current leakage". Current leakage in a polycrystalline silicon thin film transistor is referred to as the source-to-drain current in the off state. Current leakage in a polycrystalline silicon thin film transistor is principally a function of the unbonded regions of silicon which are inherent in grain boundaries, and are commonly referred to as "traps". The term "traps" derives from these unbonded or unpaired electrons of a silicon atom which "trap" carriers and prevent them from conducting. However, these "traps" present at grain boundaries facilitate current leakage through the material. Accordingly, the greater the number of grain boundaries (i.e., the smaller the grain size), the greater the current leakage through the material despite the material having inherent overall lower conductivity. Current leakage causes the SRAM cell to consume more power in the standby-state since the leakage has to be supplied from a power source. Such leakage is particularly adverse in laptop computers, where desired power consumption when a cell's state is not being changed should be very low to extend the battery life.
Polycrystalline thin films arc typically deposited by low pressure chemical vapor deposition which inherently results in a high density of grain boundaries. Also, the interface between the polycrystalline silicon and the gate oxide produces a large number of defects, resulting in a high interface state density. These defects degrade transistor performance in terms of high subthreshold slope and leakage current. This, in turn, has deleterious effects on the standby power dissipated in the integrated circuits incorporating these devices.
It would be desirable to improve upon prior art thin film transistor constructions and polycrystalline thin films.